YASIPO

electrical engineer · full-stack · ai systems4+ years

<about me/>—whoami.ts● utf-8

whoami.tstypescript

1// who I am — the short version
2 
3const engineer = {
4  name: "Yazmin",
5  role: "Engineer & Digital Architect",
6  based: "Athens, Greece",
7  origin: "the transistor level",
8  now: "full-stack + AI systems",
9};
10 
11/*
12 * I bridge silicon and software. I started with
13 * circuits, timing and FPGAs — then carried that
14 * same discipline up the stack into production
15 * apps and autonomous AI agents.
16 */
17export default engineer;

available for select contracts17 lines · typescript

signal_path // timeline

NTUA · electrical & computer engineering

FPGA, digital design & signal paths

Production full-stack architectures

Autonomous AI agent workflows

01 // academic_foundation

I am an Electrical and Computer Engineering student at the National Technical University of Athens (NTUA) — obsessed with digital systems, computer architecture, and signal processing. Every abstraction I study is grounded in physical reality: timing, power, noise, and structure.

silicon discipline

Every abstraction starts with timing, power, and physical constraints — not the other way around.

production intent

Code is shipped, monitored, and maintained — prototypes are stepping stones, not destinations.

agent-native craft

Building systems where AI agents operate with clear boundaries, tools, and observability.

02 // logic_&_stack

I carry that discipline into high-performance full-stack architectures and autonomous AI agent workflows. Low-level hardware fluency gives me an edge writing hyper-optimized application logic — from FastAPI services to Next.js production systems that stay clean under load.

›export async function initializeCore(config: CoreConfig) {›const registry = new TelemetryRegistry(bus);›await registry.sync({ timeout: 5000 });›interface AgentNode { id: string; tools: ToolSet; }›return NextResponse.json({ status: 'optimized' });›module RISCV_Core (clk, rst_n, pc);›export async function initializeCore(config: CoreConfig) {›const registry = new TelemetryRegistry(bus);›await registry.sync({ timeout: 5000 });›interface AgentNode { id: string; tools: ToolSet; }›return NextResponse.json({ status: 'optimized' });›module RISCV_Core (clk, rst_n, pc);

›interface AgentNode { id: string; tools: ToolSet; }›module RISCV_Core (clk, rst_n, pc);›const registry = new TelemetryRegistry(bus);›return NextResponse.json({ status: 'optimized' });›export async function initializeCore(config: CoreConfig) {›await registry.sync({ timeout: 5000 });›interface AgentNode { id: string; tools: ToolSet; }›module RISCV_Core (clk, rst_n, pc);›const registry = new TelemetryRegistry(bus);›return NextResponse.json({ status: 'optimized' });›export async function initializeCore(config: CoreConfig) {›await registry.sync({ timeout: 5000 });

03 // skill_topology

<skills topology/>

establishing core connections…

corentua_sys

Verilog

VHDL

FPGA

C / C++

Microcontrollers

PCB Design

Python

RTOS

Linux Kernel

Bash

System APIs

Next.js

React

Flask

PostgreSQL

TypeScript

Tailwind

hardware core

VerilogVHDLFPGAC / C++MicrocontrollersPCB Design

system logic

PythonRTOSLinux KernelBashSystem APIs

app layer

Next.jsReactFlaskPostgreSQLTypeScriptTailwind

eof // system trace completed